1. Field of the Invention
The present invention relates to a semiconductor device including an interconnection substrate on which a semiconductor chip is mounted and, in particular, to a technique effectively applicable to a semiconductor device including a center-pad-type semiconductor chip.
2. Description of the Related Art
Apparatuses containing semiconductor devices have become increasingly multifunctional and powerful. With the expansion of functionality of the apparatuses containing semiconductor devices has come a demand for higher-density semiconductor chips. The improvement of performance of the apparatuses containing semiconductor devices requires increase of the speed of semiconductor chips.
Increase of the packaging density of semiconductor chips leads to increase in the number of package pins. In addition, it is essential for techniques for increasing the speed of semiconductor chips to stabilize power supply to the semiconductor chips.
In general, a well-known technique for stably supplying power to semiconductor chips is to divide power supply. That is, multiple power-supply pads are provided and power is supplied through each of the pads.
In other words, increase of both packaging density and performance of semiconductor chips leads to a high pin count.
There is a demand for a high-density packaging technique that enables mounting of high-pin-count semiconductor chips.
Japanese Patent Application Laid-Open No. 2002-270653 discloses a technique for increasing the density of interconnections on an interconnection substrate (interposer) on which a semiconductor chip is to be mounted.
However, the existing technique described above increases the size of an interconnection substrate and semiconductor device when the number or density of pads is further increased.